1. Field of Invention
The present invention relates to a type of non-volatile memory. More particularly, the present invention relates to a silicon nitride read-only-memory and fabricating method thereof.
2. Description of Related Art
Non-volatile memory such as electrically erasable programmable read-only-memory (EEPROM) is a versatile storage device that can be activated to receive input data, read out stored data or erase stored data repeatedly. Moreover, data stored inside a non-volatile memory will not be erased even if the power supply to the memory is cut off. Hence, EEPROM is a widely adopted memory device used inside most personal computers and electronic equipment.
A conventional EEPROM has a floating gate and a control gate typically fabricated using doped polysilicon. To program the memory, electrons injected into the floating gate will be distributed evenly across the entire polysilicon layer. However, if the tunneling oxide layer under the floating gate contains defects, leakage current may flow from the device leading to reliability problems.
To prevent leakage current in the EEPROM device, a charge-trapping layer is used in place of the polysilicon floating gate. The charge-trapping layer is a silicon nitride layer, for example. In general, the silicon nitride charge-trapping layer is sandwiched between an upper and a lower silicon oxide layer so that the upper oxide layer, the nitride layer and the lower oxide layer together form an oxide/nitride/oxide (ONO) composite stack gate structure. An EEPROM having such a stacked gate structure is often referred to as a nitride read-only-memory (NROM). When a voltage is applied to the control gate and the source/drain of the device to program the memory, hot electrons are generated in a channel region close to the drain terminal. These hot electrons will inject into the charge-trapping layer. Since the silicon nitride layer has the capacity to trap electrons, electrons injected into the charge-trapping layer will be collected within a localized region instead of distributing evenly across the entire charge-trapping layer. The trapping of electrons within a localized region of the charge-trapping layer leads to a small leakage current because localized electrons have a sensitivity towards defects within the tunnel oxide layer.
Another advantage of having a silicon nitride read-only-memory is that the source/drain region on one side of the stacked gate may receive a higher voltage during programming so that electrons are injected into the silicon nitride layer closer to the other source/drain region or vice versa. By adjusting the control gate and the voltage applied to the source/drain region on each side of the control gate, the silicon nitride layer may contain two batches of electrons, a single batch of electrons or none at all. Consequently, altogether four different storage states can be written into a single nitride read-only-memory cell. In other words, the NROM is a type of 2-bit/cell non-volatile storage memory.
However, the hot electrons injected into the charge-trapping layer of the conventional 2-bit/cell NROM during a programming step will result in an electron distribution curve according to the injection energy level. When two batches of electrons are injected into a memory cell to represent two bits, the electrons within each batch may affect the other through the so-called electron secondary effect. This leads to a widening of each charge distribution curve and their eventually linking up with each other. As a result, the distribution curve that results from injecting holes into the charge-trapping layer may not overlap with the electron distribution curve during an erase operation. In other words, either the data bit is not fully erased or else a longer period is required.
Furthermore, the hot holes are injected into the charge-trapping layer through the drain side (or the source side) in a hot hole erasing operation. Since the number of holes injected into the charge-trapping layer is difficult to control, too many or too few holes may be injected into the charge-trapping layer leading to over-erase or under-erase of data. If over-erase or under-erase occurs too frequently, reliability of the memory device will be severely compromised.